Computer science and engineering Computer organization & architecture 2017

Computer Organization and Architecture Question

Sub Code: - 1618304

2017(Odd)

Time : 3Hrs

Sem. III(New)

COA (CSE)  

Full Marks : 70

Pass marks : 28

                                                                                                                                                                   

Group A

Choose the most suitable answer from the following options: -   (1*20=20)

(i) Which of the following is lowest in memory hierarchy?
(a) Cache memory
(b) Secondary memory
(c) Register
(d) RAM

(ii) Cache memory acts between
(a) CPU and RAM
(b) RAM and ROM
(c)  CPU and Hard disk
(d) None

(iii) The technique where the controller is given access to main memory is
(a) cycle stealing
(b) memory stealing
(c) burst mode
(d) none of these

(iv) Interrupts initiated by an instruction is called as-
(a) Internal
(b) external
(c) hardware
(d) software

(v) The ALU makes use of _________ to store the intermediate results. 
(a) Accumulators
(b) registers
(c) heap
(d) stack

(vi) The DMA transfer is initiated by-
(a) processor
(b) the process
(c) I/O devices
(d) OS

(vii) The universal gate is-
(a) NAND
(b) OR
(c) AND
(d) NOT

(viii) Which of the following flip-flops is used for counter?
(a) JK flip-flop
(b) T flip-flop
(c) SR flip-flop
(d) D flip-flop

(ix) ________ are numbers and encoded character generally used as operands 
(a) Input
(b) Data
(c) Information
(d) Stored values 

(x) ______ bus structure is usually used to connect I/O devices.
(a) single bus
(b) multiple bus
(c) star bus
(d) ram bus

(xi) Cycle is used in _______
(a) DMA
(b)Pipe-lining
(c) Register
(d) None of these

(xii) DMA stands for_____
(a) Direct Memory Address
(b) Direct Main Address
(c) Direct Memory Access
(d) Device Memory Access

(xiii) Combinational circuit depends only on_______
(a) present input
(b) past output
(c) both present and past 
(d) none of the above

(xiv) The addressing mode where address of Data is stored in CPU register
(a) register direct
(b) register indirect
(c) immediate
(d) None of the above

(xv) CICS stand for________
(a) Control Instruction Set Content
(b) Control Instruction Set Computer
(c) Complex Instruction Set Conversion
(d) Complex Instruction Set Computer

(xvi) Which of the following is responsible for coordinating various operations using timing signals?
(a) ALU 
(b) CU
(c) Input unit
(d)Output unit

(xvii) The correspondence between  the main memory blocks and those in the cache is specified by-
(a) mapping function
(b) replacement algorithm
(c) nitrate
(d) miss penalty

(xviii) The register that keeps track of the address of the next instruction to be executed is-
(a) AC
(b) PC
(c) IR
(d) AR

(xix) What is stored in the stack pointer
(a) operations 
(b) addressing method
(c) Stack data values
(d) address of the top item

(xx) Multiplexer consist of how many number of outputs?
(a) only one
(b) no output
(c) two output
(d) four output

Group B

➥ Answer all Five Questions: -   (5*4=20)                                                      
  
 1. Discuss about encoder in brief.

OR

 Explain about various logic gates in brief.

  2. Discuss about memory mapped I/O.

 OR

 Differentiates between SRAM and DRAM.

  3. Why flip-flops are used ? Discuss about D- flip-flop ?

  OR

 What do mean by logical address and physical address space ?
  
  4. What do mean by instruction cycle , machine cycle and states ?

   OR 

   Using 2`s compliment perform the following
        (a) 26-(-4)
        (b) 1-7

  5. What are the function of following register ?
         (i) PC   (ii) SP  (iii) MAR  (iv) IR 

OR

  What are the rules to perform 2`s complement subtraction , explain with the example ?

Group C

➥ Answer all five question: -         (5*6=30)                                                        

  6. Discuss the different mapping technique used in cache memory.

OR

 Explain in detail about pipe lining processing.

7. Consider the string 1,3,2,4,2,1,5,1,3,6,7,5,4,3,2,4,2,3,1,4
 find the page fault for 3 frames using FIFO and LRU.

OR

Discuss the replacement algorithm for cache memory.

  8. Explain about various I/O transfer technique.

OR

Using Booth`s algorithm solve the following -
            (a) (-18) * (-14)
     (b) (17) * (-8)
  
  9. Explain the various types of addressing mode in detain ?

  OR

What do mean by DMA ? Explain the step for DMA transfer technique.

 10. What is combinational circuit ? Explain different types of combinational circuit with logic diagram.

 OR

 What do you mean by sequential circuit ? Explain various types of  flip-flop ?

 (Note:- Update available soon, comment for any type of help) 

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{Other links
OS
https://diplomaforcse.blogspot.com/2019/08/previous-year-question-for-computer_26.html

CPTC
https://diplomaforcse.blogspot.com/2019/08/previous-year-question-for-computer_28.html

ISP: -
https://diplomaforcse.blogspot.com/2019/08/previous-year-question-for-computer_31.html

NOTES of COA (unit-1): -

https://diplomaforcse.blogspot.com/2019/09/notes-for-computer-science-engineering.html

NOTES of ISP (unit-4): -

https://diplomaforcse.blogspot.com/2019/09/notes-for-computer-science-engineering_21.html


Notes of OS (Unit- 1) {click me}

}

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